1. Field of the Embodiments
Embodiments relate to a method and/or a device which detects a seed layer. Embodiments relate to a method and/or device which form layers on a semiconductor device. A device which detects a seed layer may use an inspection device, which may check whether the seed layer is formed on top of a wafer. Detection of a seed layer may occur prior to a plating process which forms an interconnection layer. In embodiments, a seed layer detecting device forms layers on a semiconductor device.
2. Description of Related Art
In general, line widths of interconnections and the intervals between interconnections of semiconductor devices have gotten smaller through the development of semiconductor technology. Some semiconductor devices have a multi-interconnection structure including interconnections and insulating layers, which may be alternately stacked. Semiconductor devices having multi-interconnection structures may include an upper interconnection connected to a lower interconnection through a via hole formed between insulating layers.
Semiconductor devices having multi-interconnection structures may have a relatively high degree of integration and/or may have a relatively simple circuit design. A semiconductor device having multi-interconnection structures may have reduced signal delay and/or improved operational speed. Semiconductor devices with micro-size line widths may have relatively high interconnection resistance. To reduce interconnection resistance, interconnections of semiconductor devices may be fabricated using a superior electric conductivity material.
Copper (Cu) (e.g. which has a lower electric resistance than aluminum (Al)) may be used as a material for interconnections in a semiconductor device. Copper has a lower electric resistance and specific electric resistance than aluminum. However, Copper has a higher thermal conductive coefficient than aluminum. Since copper has relatively high electro migration (EM) and superior stress migration (SM) compared to aluminum, copper may be suitable for semiconductor devices having shallow line widths.
However, when copper is used in interconnections of semiconductor devices, copper may diffuse into an interlayer dielectric layer. Accordingly, copper interconnections may degrade electric characteristics and insulating characteristics of semiconductor devices.
Example FIGS. 1 and 2 are sectional views illustrating formation of an interconnection layer in a semiconductor device. As illustrated in FIGS. 1 and 2, metal layer 2 (e.g. which may serve as a barrier layer to prevent copper diffusion) may be formed over wafer 1, which may have a circuit section. Metal layer 2 may serve as a lower circuit interconnection.
Examples of materials that may be included in metal layer 2 include tungsten (W), tungsten alloys, titanium (Ti), titanium alloys, titanium nitride, tantalum (Ta), tantalum nitride, tantalum silicon nitrides, and other similar materials. Metal layer 2 may be deposited over wafer 1 by chemical vapor deposition (CVD), sputtering, or a similar process.
A copper layer (e.g. which may be a source of the copper interconnection) may be formed by an electroplating process. To form copper interconnections using electroplating, seed layer 3 may be formed over the surface of metal layer 2 (e.g. using a sputtering process). Seed layer 3 may have a thickness of about 50 Å. Pattern layer 4 may have an opening formed over the surface of seed layer 3. Electroplating may be performed on seed layer 3 (e.g. through the exposed opening of pattern layer 4) to form copper interconnection layer 5.
As illustrated in FIG. 2, pattern layer 4 may be removed after copper interconnection layer 5 has been formed. Seed layer 3 may serve as an electrode, resulting in a copper interconnection. Seed layer 3 may be formed over metal layer 2 before electroplating of seed layer 3. However, if electroplating is performed when there are irregularities in seed layer 3 and/or if seed layer 3 is not present, an underlying wafer may be damaged.